1. Field of the Invention
This invention relates generally to the manufacture of high performance semiconductor devices. More specifically, this invention relates to a process for the manufacture of high performance semiconductor devices in which the threshold voltage of parasitic transistors is increased to prevent turn-on of the parasitic transistors during normal operation of the semiconductor device.
2. Discussion of the Related Art
Properly functioning electrical circuits require isolated devices that are connected through specific electrical paths. When fabricating silicon integrated circuits, it must be possible to electrically isolate devices built into the silicon from one another. These isolated devices can then be selectively interconnected to create the specific electrical circuit required. Because of the requirement for isolation of devices in a silicon substrate, isolation technology in one of the most important technologies is semiconductor manufacturing. Because bipolar integrated circuits were the first to be developed, a technology for isolating the collector regions in the bipolar devices was the first to be developed and was called junction isolation. PMOS and NMOS devices do not need junction isolation, but they do need an isolation structure that would prevent the establishment of parasitic channels between adjacent devices. The most important technique developed to establish isolation between adjacent devices is LOCOS isolation (LOCal Oxidation of Silicon). LOCOS technology involves the formation of semirecessed oxide regions in the nonactive (or field) regions of the substrate. CMOS devices require that isolation exist between devices in adjacent tubs as well as between devices within each tub.
As device geometry has reached the submicron region, conventional LOCOS isolation technologies reached the limits of their effectiveness, and alternative isolation processes for CMOS and bipolar technologies were needed. Modified LOCOS processes overcame some of the drawbacks of conventional LOCOS for some small-geometry devices. Other processes, such as trench isolation and selective-epitaxial isolation were developed.
Because MOS transistors are self-isolated and as long as the source-substrate and drain-substrate pn-junctions are held at reverse bias, the drain current should only be due to current flow from source to drain through a channel under the gate. This implies that no significant current between adjacent MOS devices exists if no channel exists between them. Thus, the buried n+-p junction needed to isolate bipolar transistors is not needed to isolate MOS circuits. The self-isolation nature of MOS devices represents substantial area savings for MOS circuits as compared to junction-isolated bipolar circuits and is one of the reasons for the shift to MOS devices by the semiconductor industry. Thus, integrated circuits having the highest component densities are fabricated with MOS technologies.
However, the phenomenon of parasitic transistor formation is a problem in MOS devices. The method that components are interconnected in an integrated circuit involves the fabrication of metal stripes that run across the oxide in the regions between the transistors. These metal stripes form the gates of parasitic MOS transistors, with the oxide beneath them forming a gate oxide and the diffused regions on either side of the oxide acting as the source and drain. In order for the parasitic transistors not to disrupt the operation of the MOS device, the threshold voltage of the parasitic transistor must be kept higher than any possible operating voltage so that spurious channels will not be formed between devices.
Therefore, to effectively isolate MOS transistors, it is necessary to prevent the formation of channels in the field regions. This implies that a large value of threshold voltage for the parasitic transistor is needed in the field regions. It has been determined that the threshold voltage of the field regions needs to be 3-4 volts above the supply voltage to ensure that less than 1 picoampere of current flows between isolated MOS devices. Therefore, for effective isolation in a circuit with a supply voltage of five volts, the minimum field-region threshold voltage must be in the range of 8-9 volts. Non-volatile circuits have higher programming voltages than the normal supply voltages and can reach 14-15 volts. Another factor that has a strong effect on the threshold voltage is the polarity of the charge present in the interlevel dielectric. A positive charge in the interlevel dielectric reduces the threshold voltage and a negative charge increases the threshold voltage.
Two of the methods developed for raising the threshold voltage in a normal (non-parasitic) MOS transistor have been used to increase the field region threshold voltage (of the parasitic transistors). These involve increasing the field oxide thickness and raising the doping beneath the field oxide. As can be appreciated, if the field oxide was made sufficiently thick, it alone could cause a high enough threshold voltage in the parasitic transistor to prevent it from turning on. However, this gives rise to step coverage problems and reduced field-oxide thicknesses are preferred. To achieve a sufficiently large field threshold voltage with the thinner field oxides, the doping under the field oxide must be increased.
The field oxide is typically made seven to ten times thicker than the gate oxide in the active regions. The thick field oxide also has the beneficial effect of reducing the parasitic capacitance between interconnect runners and the substrate, improving the speed characteristics of the integrated circuit. Normally, ion implantation is used to increase the doping under the field oxide. This ion implantation process is called a "channel-stop implant." The combination of thick oxides and channel-stop implants can provide adequate isolation for PMOS and NMOS integrated circuits. However, additional isolation considerations for CMOS circuits are necessary. In CMOS devices, like kinds of devices within a given well must be isolated in the same manner as the devices in either NMOS or PMOS devices, that is, through a combination of a thick field oxide and channel-stop doping. However, the isolation requirement of CMOS technology is greater because it is also necessary to isolate the p- and n-channel devices from one another. This additional isolation requirement must satisfy two requirements: (1) any possible leakage currents that could flow between adjacent PMOS and NMOS devices must be suppressed; and (2) the susceptibility of the CMOS devices to latchup must be minimized. The added requirement for the isolation of p- and n-channel devices has a penalty because such isolation requires more area than between like types of devices. The large area penalty of p- and n-channel device isolation is one reason why CMOS technologies using conventional isolation methods cannot achieve as high a packing density as NMOS.
Therefore, what is needed is a method of increasing the threshold voltage of MOS devices without increasing the field oxide thickness.